Area fill synthesis for uniform layout density

Chemical-mechanical polishing (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on local characteristics of the layout. To improve manufacturability and performance predictability, we seek to make a layout uniform with respect to prescribed density criteria, by inserting “area fill” geometries into the layout. In this paper, we make the following contributions. First, we define the flat, hierarchical and multiple-layer filling problems, along with a unified density model description. Secondly, for the flat filling problem, we summarize current linear programming approaches with two different objectives, i.e., the Min-Var and Min-Fill objectives. We then propose several new Monte-Carlo based filling methods with fast dynamic data structures. Third, we give practical iterated methods for layout density control for CMP uniformity based on linear programming, Monte-Carlo and greedy algorithms. Fourth, to address the large data volume and inherent lack of scalability of flat layout density control, we propose practical methods for hierarchical layout density control. These methods smoothly trade off runtime, solution quality, and output data volume. Finally, we extend the linear programming approaches and present new Monte-Carlo based methods for the multiple-layer filling problem. Comparisons with previous filling methods show the advantages of the new iterated Monte-Carlo and iterated greedy methods for both flat and hierarchical layouts, and for both density models (spatial density and effective density). We achieve nearoptimal filling for flat layouts with respect to each of these objectives. Our experiments indicate that the hybrid hierarchical filling approach is efficient, scalable, accurate, and highly competitive with existing methods (e.g., linear-programming based techniques) for hierarchical layouts. This research was supported by a Packard Foundation Fellowship, by the MARCO Gigascale Silicon Research Center, by NSF Young Investigator Award MIP-9457412, by NSF grant CCR-9988331, and by a grant from Cadence Design Systems, Inc. Y. Chen is with the Department of Computer Science, UC Los Angeles, Los Angeles, CA 90095-1596. E-mail: [email protected]. A. B. Kahng is with the Departments of Computer Science and Engineering, and of Electrical and Computer Engineering, UC San Diego, La Jolla, CA 92093-0114. E-mail: [email protected]. G. Robins is with the Department of Computer Science, University of Virginia, Charlottesville, VA 22903-2442. E-mail: [email protected]. A. Zelikovsky is with the Department of Computer Science, Georgia State University, Atlanta, GA 30303. E-mail: [email protected].